1. Field of the Invention
The present invention relates, generally, to an apparatus for receiving digital signals and, more specifically, to developing system clock signals from a digital signal received via a digital audio interface, for instance.
2. Description of the Prior Art
In commercial digital audio equipment a standardized interface for transmitting a digital audio signal has been proposed, and FIG. 1 represents a signal format of this digital audio interface. It is assumed that a period Ts, which is the inverse of the sampling frequency Fs of the digital audio signal, represents one frame. Data of the left channel is arranged in the first half period of the frame, while data of the right channel is arranged in the latter half period thereof. One half of the frame is called a subframe, and into this subframe 32 bits of data are inserted.
A four-bit preamble is positioned at the head of each subframe, four-bit auxiliary data AUX is then arranged, and 20-bit digital audio data is inserted next to the data AUX starting from its least significant bit (LSB). A four-bit control signal V, U, C, P is added after the audio data. The control signal (V: valid flag, U: user data, C: channel status, P: parity bit) is used to indicate whether data is valid or invalid, whether digital copying is prohibited, the sampling frequency, etc. Twenty-eight bits, except for the four-bit preamble, are subjected to bi-phase modulation, and the preamble is subjected to digital modulation by a method other than bi-phase modulation.
In an apparatus for receiving a digital signal having the above-described signal format, it is necessary to develop system clocks in synchronism with the reception signal using a phase-locked loop (PLL) in order to perform digital demodulation, data extraction, etc. Specifically, a signal with a frequency of 2Fs in synchronism with the preamble in the received digital signal is supplied to the PLL as a reference signal.
Conventionally, the reference signal for the PLL is developed from a received signal by a specialized circuit, such as the one shown in FIG. 2. FIG. 3 is a waveform diagram representing the timing of the signals in the circuit of FIG. 2.
In FIG. 2, an input terminal 41 receives a digital signal RX having a signal format of a digital audio interface. The input digital signal RX is supplied to an edge detector 42, and an edge pulse signal E0 in which pulses are respectively generated at the timing of the leading and trailing edges of the signal RX is produced.
The edge pulse signal E0 carrying leading and trailing edge information is supplied to a retriggerable monostable-multivibrator 43, which is triggered at the leading edge of the pulses in edge pulse signal E0, and a pulse signal WNl is produced. The pulse signal WNl is a signal having a low level for a period of time from the leading edge of the pulses in edge pulse signal E0. The output signal WN1 of multivibrator 43 is supplied to a second retriggerable monostable-multivibrator 44, and a pulse signal WN2 that has a low level for a predetermined period from the falling edge of the pulses in signal WN1 is generated. Signal WN2 has a frequency (2Fs) that is twice the sampling frequency Fs of the input digital signal, and is fed to a phase-locked loop (PLL) 45 as a reference signal. System clock signals in synchronism with the input digital signal RX are produced at an output terminal 46 of PLL 45.
The preamble of the input digital signal RX may have six kinds of bit patterns depending on the value (0 or 1) of the last symbol in an immediately preceding subframe and the method employed to send two-channel stereo. That is, a set of three preambles is used and the preamble preceding each digital audio sample should indicate the beginning of a sample: of channel A and of a block; of channel A and not a block; or of channel B, C, etc. but not A. A set of three different preambles is used to provide the six different bit patterns. In the example of a preamble in the signal RX as shown in FIG. 3, the inversion intervals are (3T, 3T, T, T). T is a time period derived as the inverse of the sampling frequency equal to 128 Fs. As a result, to develop a signal in synchronism with the digital signal RX, it is necessary to detect the 3T-period (pulse width) of the signal RX. In the circuit of FIG. 2, monostable multivibrator 43 detects this 3T-period.
There may be three different sampling frequencies Fs of the input digital signal RX, for example, 32 kHz, 44.1 kHz, 48 kHz. The pulse width of 2T in the case where Fs equals 44.1 kHz and the pulse width of 3T in the case where Fs equals 48 kHz are comparatively close values. For this reason, in the conventional structure for determining both of them using the time constant of the monostable multivibrator, there is a possibility that a preamble can be erroneously detected due to variations of values of components, and value changes due to temperature variations, for example. Also, the conventional approach described above using a number of monostable-multivibrators is not suited for integrated circuit (IC) fabrication.